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copyright?2010-2011 fujitsu semiconductor limited all rights reserved 2011.3 fujitsu semiconductor data sheet 8-bit proprietary microcontrollers cmos f 2 mc-8fx MB95R203A MB95R203A description the MB95R203A is general-purpose, single-chip microc ontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? f 2 mc-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test branch instruction ? bit manipulation instructions etc. ? clock ? selectable main clock source main osc clock (up to 10 mhz, maximu m machine clock frequency is 5 mhz) external clock (up to 20 mhz, maximu m machine clock frequency is 10 mhz) internal main cr clock (typ 1/8 mhz, maximum machine clock frequency is 8 mhz) ? selectable sub clock source sub osc clock (32 khz) sub internal cr clock (typ : 100 khz, min : 50 khz, max : 200 khz) (continued) ds07-12630-2e
MB95R203A 2 ds07-12630-2e (continued) ? timer ? 8/16-bit compound timer ? time-base timer ? watch prescaler ? uart/sio ? offers clock asynchronous (uart) or clock synchronous (sio) serial data transfer ? full duplex double buffer ? i 2 c ? built-in wake-up function ? external interrupt ? interrupt by the edge detection (sel ect rising edge/falling edge/both edges) ? can be used to recover from low-power consumption modes (also called standby mode) ? 8/10-bit a/d converter ? 8-bit or 10-bit resolutions can be selected ? low-power consumption (standby) mode ? stop mode ? sleep mode ? watch mode ? time-base timer mode ? i/o port : 16 ? general-purpose i/o ports : cmos i/o : 12, n-ch open drain : 4 ? on-chip debug ? 1 wire serial control ? support serial writing. (asynchronous mode) ? hardware/software watch dog timer ? built-in hardware watchdog timer ? low voltage detection circuit (lvd) ? low voltage detection reset circuit ? low voltage detection interrupt circuit ? circuit to monitor fram power supply ? clock supervisor counter (csv) ? built-in clock supervise function ? programmable input voltage levels of port ? cmos input level / hysteresis input level ? fram ? non-volatile memory ? 8 kbytes of fram integrated on-chip ? fram memory security function ? protects the content of fram memory
MB95R203A ds07-12630-2e 3 product overview (continued) part number parameter MB95R203A rom (fram) capacity 8 kbytes ram capacity 496 bytes reset output yes low voltage detection reset yes cpu function number of basic instructions instruction bit length instruction length data bit length minimum instruction execution time interrupt processing time : 136 instructions : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 100 ns (at machine clock 10 mhz) : 0.9 s (at machine clock 10 mhz) port general-purpose i/o ports : 16 cmos i/o : 12, n-ch open drain : 4 time-base timer interrupt cycle : 0.256 ms to 8.3 s (at external 4 mhz) hardware/software watchdog timer reset generation cycle main clock at 10 mhz : 105 ms (min) sub clock cr can be used as the watch dog source clock. wild registers it can be used to replace three bytes of data. uart/sio able to transfer data using uart/sio variable data length (5/6/7/8-b it) , built-in baud rate generator transfer rate (2400 bps to 125000 bps at 10 mhz) , full-duplex transfers with built-in double buffers nrz type transfer format, error detection function lsb-first or msb-first can be selected capable of clock synchronous (sio) or cl ock asynchronous (uart) serial data transfer i 2 c bus transmit and receive master/slave bus function, arbitration function, transfer direction detection function start condition repeated genera tion and detection functions built-in timeout detection function 8/10-bit a/d converter 6 ch 8-bit or 10-bit resolution can be selected 8/16-bit compound timer 2 ch can be configured as a 2 ch 8-bit timer or 1 ch 16-bit timer built-in timer function, pwc function, pwm function and capture function count clock : available from internal clocks (7 types) or external clocks with square wave output external interrupt 6 ch interrupt by edge detection (selec t rising edge/falling edge/both edges) can be used to recover from standby modes low voltage interrupt selectable from 4 kinds of low voltage detection levels usable as a release function from standby mode
MB95R203A 4 ds07-12630-2e (continued) part number parameter MB95R203A on-chip debug 1 wire serial control support serial writing. (asynchronous mode) watch prescaler eight different time intervals can be selected. fram non-volatile memory number of read/write cycles : 10 15 times data retention characteristics : 10 years ( + 55 c) read security function function to monitor fram power supply standby mode sleep mode, stop mode, watch mode, time-base timer mode package dip-24, sop-20
MB95R203A ds07-12630-2e 5 pin assignment (top view) (dip-24p-m07) (top view) (fpt-20p-m09) x0 nc x1 vss x1a/pg2 x0a/pg1 vcc scl/p65 rst/pf2 to10/p62 nc to11/p63 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p12/ec0/dbg nc p07/int07 p06/int06/to01 p05/int05/an05/to00/hclk2 p04/int04/an04/ui/hclk1/ec0 p03/int03/an03/uo p02/int02/an02/uck p01/an01 p00/an00 nc p64/ec1/sda 24pin (dip-24) *the number of usable pins is 20. x0 x1 vss x1a/pg2 x0a/pg1 vcc scl/p65 rst/pf2 to10/p62 to11/p63 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00/hclk2 p04/int04/an04/ui/hclk1/ec0 p03/int03/an03/uo p02/int02/an02/uck p01/an01 p00/an00 p64/ec1/sda 20pin (sop-20)
MB95R203A 6 ds07-12630-2e pin description (continued) pin no. pin name i/o circuit type * function dip24 sop20 1 1 x0 b main clock input oscillation pin 3 2 x1 b main clock input/output oscillation pin 43 vss ? power supply pin (gnd) 5 4 pg2/x1a c general-purpose i/o port this pin is also used as sub clock input/output oscillation pin. 6 5 pg1/x0a c general-purpose i/o port this pin is also used as sub clock input oscillation pin. 76 vcc ? power supply pin 8 7 p65/scl i general-purpose i/o port this pin is also used as i 2 c clock i/o. 98 pf2/rst a general-purpose i/o port this pin is also used as reset pin 10 9 p62/to10 d general-purpose i/o port high current port this pin is also used as 8/16-bit compound timer ch.1 output. 12 10 p63/to11 d general-purpose i/o port high current port this pin is also used as 8/16-bit compound timer ch.1 output. 13 11 p64/sda/ec1 i general-purpose i/o port this pin is also used as i 2 c data i/o. this pin is also used as 8/16-bit compound timer ch.1 clock input. 15 12 p00/an00 e general-purpose i/o port this pin is also used as a/d converter analog input. 16 13 p01/an01 e general-purpose i/o port this pin is also used as a/d converter analog input. 17 14 p02/int02/an02/ uck e general-purpose i/o port this pin is also used as external interrupt input. this pin is also used as a/d converter analog input. this pin is also used as uart/sio clock i/o. 18 15 p03/int03/an03/ uo e general-purpose i/o port this pin is also used as external interrupt input. this pin is also used as a/d converter analog input. this pin is also used as uart/sio data output. 19 16 p04/int04/an04/ ui/hclk1/ec0 f general-purpose i/o port this pin is also used as external interrupt input. this pin is also used as a/d converter analog input. this pin is also used as uart/sio data input. this pin is also used as 8/16-bit compound timer ch.0 clock input.
MB95R203A ds07-12630-2e 7 (continued) * : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function dip24 sop20 20 17 p05/int05/an05/ to00/hclk2 e general-purpose i/o port high current port this pin is also used as external interrupt input. this pin is also used as a/d converter analog input. the pins are also used as 8/16-bit compound timer ch.0 output. this pin is also used as the external clock input. 21 18 p06/int06/to01 g general-purpose i/o port high current port this pin is also used as external interrupt input. this pin is also used as 8/16-bit compound timer ch.0 output. 22 19 p07/int07 g general-purpose i/o port this pin is also used as external interrupt input. 24 20 p12/ec0/dbg h general-purpose i/o port this pin is also used as dbg input pin. this pin is also used as 8/16-bit compound timer ch.0 clock input. 2, 11, 14, 23 ? nc ? internal connect pin. be sure this pin is left open.
MB95R203A 8 ds07-12630-2e i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance : approx. 1 m ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance : approx. 10 m ?cmos output ? hysteresis input ? with pull-up control d ? cmos output ? hysteresis input n -ch reset input / hysteresis input reset output / digital output x0 x1 standby control clock input x1a x0a n-ch p-ch n-ch p-ch r p-ch r port select pull-up control digital output digital output standby control hysteresis input clock input standby control / port select port select pull-up control digital output digital output standby control hysteresis input clock input digital output n -ch p-ch digital output standby control hysteresis input digital output
MB95R203A ds07-12630-2e 9 (continued) type circuit remarks e ? cmos output ? hysteresis input ? with pull-up control f ? cmos output ? hysteresis input ? cmos input ? with pull-up control g ? cmos output ? hysteresis input ? with pull-up control h ? n-ch open drain output ? hysteresis input i ? n-ch open drain output ? cmos input ? hysteresis input n -ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output analog input a/d control standby control hysteresis input cmos input digital output n -ch p-ch p-ch r pull-up control digital output digital output hysteresis input standby control n -ch hysteresis input digital output n -ch digital output cmos input hysteresis input standby control
MB95R203A 10 ds07-12630-2e notes on device handling ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not exceeded when they are used. latch-up may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withst and voltage pins or if higher than t he rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the vcc power-supply voltage. for stabilization, in principle, keep the variation in vcc ripple (p-p value) in a commercial frequency range (50 hz / 60 hz) not to exceed 10% of the standard vc c value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a momentary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabiliz ation wait time is required for power-on reset, wake- up from sub clock mode or stop mode. ? do not use a sample used in progra m development as mass-produced product.
MB95R203A ds07-12630-2e 11 pin connection ? treatment of unused input pin leaving unused input pins unconnected can cause a bnormal operation or latch-up, leaving to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k . any unused input/output pins may be set to output mode and le ft open, or set to input mode and treated the same as unused input pins. if there is unused output pin, make it to open. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. howeve r, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the to tal output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 f between v cc and v ss near this device. ? dbg pin connect the dbg pin directly to external pull-up. to prevent the device unintentionally entering test mo de due to noise, lay out the printed circuit board so as to minimize the distance from the dbg pin to v cc or v ss pins. the dbg pin should not stay at ?l? level afte r power-on until the reset output is released. ? rst pin connect the rst pin directly to pull-up. to prevent the device unintentionally entering test mo de due to noise, lay out the printed circuit board so as to minimize the distance from the rst pin to v cc or v ss pins. the rst /pf2 pin functions as the reset input/output pin af ter power-on. in addition, the reset output can be enabled by the rstoe bit of the sysc register, and the reset input function or the general purpose i/o function can be selected by the rsten bit of the sysc register. r dbg rst r ? example of dbg / rst connection diagram pull-up resistor recommended resistance for dbg pin : r = 4.7 k for rst pin : r = 10 k
MB95R203A 12 ds07-12630-2e notes on on-chip debug ? although the [upload flash memory] button on s oftune tm * workbench is enabled, clicking it does not start the actual processing. ? when you click on the [erase flash memory] button on s oftune workbench, data is overwritten into the fram area, as shown below. ? when you click on the [erase flash memory] and the [target load] button on s oftune workbench, data in the i/o area described below is undefined. ? be very careful not to apply voltages to the pins pf2/rst in excess of the absolute maximum ratings. especially when handling devices in the environment compatible to the package, such as mb95200h/ 210h and so on, the voltage may be err oneously applied to the pins pf2/rst in excess of the maximum rating and it may cause thermal breakdown of the device. * : softune is a trademark of fujit su semiconductor limited, japan. address data to be overwritten f554 h 55 h faaa h a0 h ffbc h indeterminate ffbd h indeterminate entire fram except the above ff h address data to be overwritten 0070 h indeterminate 0071 h indeterminate
MB95R203A ds07-12630-2e 13 block diagram pf2* 1 /rst* 2 x1 x0 p12* 1 /dbg p02/i n t02 to p07/i n t07 p65* 1 /scl* 1 p64* 1 /sda* 1 pg2/x1a* 2 pg1/x0a* 2 (p02/uck) (p04/ui) (p03/uo) (p05* 3 /to00) (p06* 3 /to01) p12/ec0(p04/ec0) p62* 3 /to10 p63* 3 /to11 (p64/ec1) port (p00/a n 00 to p05/a n 05) fram ( 8 k b ytes) w ith sec u rity ram (496 b ytes) l v d reset cr oscillator clock control oscillator circ u it on-chip de bu g w ild register external interr u pt 8 /16- b it compo u nd timer (0) 8 /16- b it compo u nd timer (1) i 2 c 8 /10- b it a/d con v erter uart/sio port f 2 mc- 8 fx cpu *1 : p12, p64, p65 and pf2 are n -ch open drain. *2 : soft w are option *3 : p05, p06, p62 and p63 are high c u rrent ports. v cc v ss
MB95R203A 14 ds07-12630-2e cpu core memory space memory space of the MB95R203A is 64 kbytes and cons ists of i/o area, data area, and program area. the memory space includes special-purpose areas such as the general-purpose registers and vector table. memory map of the MB95R203A shown below. ? memory map i/o - ram 496 byte register - extension i/o - fram 8 kb MB95R203A 0000 h 00 8 0 h 0090 h 02 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h e000 h ffff h
MB95R203A ds07-12630-2e 15 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ?? 0007 h sycc system clock control register r/w xxxxxx11 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch timer control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ?? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0027 h ? (disabled) ?? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ?? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 cont rol status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 cont rol status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 cont rol status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 cont rol status register 1 ch.1 r/w 00000000 b
MB95R203A 16 ds07-12630-2e (continued) address register abbreviation register name r/w initial value 003a h to 0046 h ? (disabled) ?? 0047 h lvdcr low voltage detection interrupt control register r/w 00000000 b 0048 h ? (disabled) ?? 0049 h eic10 external interrupt circuit c ontrol register ch.2/ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit c ontrol register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit c ontrol register ch.6/ch.7 r/w 00000000 b 004c h to 0055 h ? (disabled) ?? 0056 h smc10 uart/sio serial mode control register 1 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 r/w 00100000 b 0058 h ssr0 uart/sio serial status and data register r/w 00000001 b 0059 h tdr0 uart/sio serial output data register r/w 00000000 b 005a h tdr0 uart/sio serial input data register r/w 00000000 b 005b h to 005f h ? (disabled) ?? 0060 h ibcr00 i 2 c bus control register 0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register r/w 00000000 b 0063 h iddr0 i 2 c data register r/w 00000000 b 0064 h iaar0 i 2 c address register r/w 00000000 b 0065 h iccr0 i 2 c clock control register r/w 00000000 b 0066 h fscr fram status/control register r/w 00000000 b 0067 h frac fram register access control register r/w 00000000 b 0068 h fabh fram write permit start address register (h) r/w 11111111 b 0069 h fabl fram write permit start address register (l) r/w 11111111 b 006a h fash fram write permit area size register (h) r/w 00000000 b 006b h fasl fram write permit area size register (l) r/w 00000000 b 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b 0070 h fvah fram violation addre ss register (h) r xxxxxxxx b 0071 h fval fram violation address register (l) r xxxxxxxx b
MB95R203A ds07-12630-2e 17 (continued) address register abbreviation register name r/w initial value 0072 h to 0075 h ? (disabled) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? register bank pointer (rp) , mirror of direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 cont rol status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 cont rol status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 cont rol status register 0 ch.1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 cont rol status register 0 ch.1 r/w 00000000 b
MB95R203A 18 ds07-12630-2e (continued) ? r/w access symbols ? initial value symbols note : do not write to the ? (disabled) ?. re ading the ? (disabled) ? returns an undefined value. address register abbreviation register name r/w initial value 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch.1 r/w 00000000 b 0f9c h to 0fbd h ? (disabled) ?? 0fbe h pssr0 uart/sio prescaler select register r/w 00000000 b 0fbf h brsr0 uart/sio baud rate setting register r/w 00000000 b 0fc0 h to 0fc2 h ? (disabled) ?? 0fc3 h aidrl a/d input disable register lower r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ?? 0fe4 h crth cr-trimming register upper r/w 1xxxxxxx b 0fe5 h crtl cr-trimming register lower r/w 000xxxxx b 0fe6 h lvdcr2 low voltage detecti on control register r/w 00000010 b 0fe7 h ? (disabled) ?? 0fe8 h sysc system control register r/w 11000-11 b 0fe9 h cmcr clock monitor control register r/w --000000 b 0fea h cmdr clock monitor data register r/w 00000000 b 0feb h wdth watchdog id register upper r/w xxxxxxxx b 0fec h wdtl watchdog id register lower r/w xxxxxxxx b 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w --00-0-- b 0fef h to 0fff h ? (disabled) ?? r/w : readable / writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
MB95R203A ds07-12630-2e 19 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch.4 irq00 fffa h fffb h l00 [1 : 0] high low external interrupt ch.5 irq01 fff8 h fff9 h l01 [1 : 0] external interrupt ch.2 irq02 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq03 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio (transmit) irq04 fff2 h fff3 h l04 [1 : 0] uart/sio (receive) 8/16-bit compound timer ch.0 (lower) irq05 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq06 ffee h ffef h l06 [1 : 0] ? irq07 ffec h ffed h l07 [1 : 0] ? rq08 ffea h ffeb h l08 [1 : 0] fram (udef, prot) irq09 ffe8 h ffe9 h l09 [1 : 0] ? irq10 ffe6 h ffe7 h l10 [1 : 0] ? irq11 ffe4 h ffe5 h l11 [1 : 0] ? irq12 ffe2 h ffe3 h l12 [1 : 0] ? irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] ? irq15 ffdc h ffdd h l15 [1 : 0] i 2 c complete/error irq16 ffda h ffdb h l16 [1 : 0] i 2 c stop/al/wakeup low voltage detection interrupt irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] time-base timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch prescaler irq20 ffd2 h ffd3 h l20 [1 : 0] ? irq21 ffd0 h ffd1 h l21 [1 : 0] 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] fram (area) irq23 ffcc h ffcd h l23 [1 : 0]
MB95R203A 20 ds07-12630-2e electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = 0.0 v. *2 : v i and vo should not exceed v cc + 0.3 v. v i must not exceed the rating voltage. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 vcc vss ? 0.3 vss + 4.0 v input voltage* 1 v i vss ? 0.3 vss + 4.0 v *2 output voltage* 1 v o vss ? 0.3 vss + 4.0 v *2 ?l? level maximum output current i ol1 ? 15 ma other than p05, p06, p62 and p63 i ol2 15 p05, p06, p62 and p63 ?l? level average current i olav1 ? 4 ma other than p05, p06, p62 and p63 average output current = operating current operating ratio (1pin) i olav2 12 p05, p06, p62 and p63 average output current = operating current operating ratio (1pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p05, p06, p62 and p63 i oh2 ? 15 p05, p06, p62 and p63 ?h? level average current i ohav1 ? ? 4 ma other than p05, p06, p62 and p63 average output current = operating current operating ratio (1pin) i ohav2 ? 8 p05, p06, p62 and p63 average output current = operating current operating ratio (1pin) ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current i ohav ?? 50 ma total average output current = operating current operating ratio (total of pins) power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 40 + 85 c
MB95R203A ds07-12630-2e 21 2. recommended operating conditions (v ss = 0.0 v) * : the normal operation is performed from 1.8 v to the low voltage detection of the fram power supply monitor, or from the release voltage of the fram power supply monitor to 1.8 v. reset is generated during the period that the low voltage detection reset has been detected. as for the low voltage detection, see ?(8) low voltage detection? in ?4. ac characteristics?. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application out side the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage vcc 1.8* 3.6 v in normal operating 2.7 3.6 in a/d converter operating 2.7 3.6 on-chip debug mode operating temperature t a ? 40 + 85 c other than on-chip debug mode + 5 + 35 c on-chip debug mode
MB95R203A 22 ds07-12630-2e 3. dc characteristics (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ih1 p04 *1 0.7 v cc ? v cc + 0.3 v when cmos input level (hysteresis input) is selected v ih2 p64, p65 *1 0.7 v cc ? v cc + 0.3 v when cmos input level (hysteresis input) is selected v ihs1 p00 to p07, p12, p62, p63, pg1, pg2 *1 0.8 v cc ? v cc + 0.3 v hysteresis input v ihs2 p64, p65 *1 0.8 v cc ? v cc + 0.3 v hysteresis input v ihm pf2 ? 0.8 v cc ? v cc + 0.3 v hysteresis input ?l? level input voltage v il p04, p64, p65 *1 v ss ? 0.3 ? 0.3 v cc v when cmos input level (hysteresis input) is selected v ils p00 to p07, p12, p62 to p65, pg1, pg2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d p12, p64, p65, pf2 ? v ss ? 0.3 ? v cc + 0.3 v ?h? level output voltage v oh1 output pins other than p05, p06, p62 to p65, pf2, p12 i oh = ? 4.0 ma 2.4 ?? v v oh2 p05, p06, p62, p63 i oh = ? 8.0 ma 2.4 ?? v ?l? level output voltage v ol1 output pins other than p05, p06, p62, p63 i ol = 4.0 ma ?? 0.4 v v ol2 p05, p06, p62, p63 i ol = 12.0 ma ?? 0.4 v
MB95R203A ds07-12630-2e 23 (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max input leak current (hi-z output leak current) i li other than ports p64, p65 0.0 v < v i < v cc ? 5 ? + 5 a when pull-up resistance is disabled open-drain output leak current i liod p64, p65 0.0 v < v i < v cc ? 4 ? + 10 a pull-up resistance r pull p00 to p07, pg1, pg2 v i = 0.0 v 16.5 33 80 k when pull-up resistance is enabled input capacitance c in other than vcc, vss f = 1 mhz ? 515pf power supply current* 2 i cc vcc (external clock operation) f ch = 20 mhz, f mp = 10 mhz main clock mode (divided by 2) ? 2.3 3.1 ma ? 4.5 6 ma at a/d conversion i ccs * 3 f ch = 20 mhz, f mp = 10 mhz main sleep mode (divided by 2) t a = + 25 c ? 1.1 1.7 ma i ccl f cl = 32 khz, f mpl = 16 khz sub clock mode (divided by 2) t a = + 25 c ? 52 280 a i ccls * 3 f cl = 32 khz, f mpl = 16 khz sub sleep mode (divided by 2) t a = + 25 c ? 15 260 a i cct * 3 f cl = 32 khz, watch mode main stop mode t a = + 25 c ? 15 240 a i ccmcr vcc f crh = 1 mhz, f mp = 1 mhz main cr clock mode ? 0.55 ? ma i ccscr sub cr clock mode (divided by 2) t a = + 25 c ? 62 320 a
MB95R203A 24 ds07-12630-2e (continued) (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : p04, p64, p65 can switch the i nput level to either the ?cmos input level? or ?hysteresis input level?. the switching of the input level can be set by the input level selection register (ilsr) . *2 : ? the power-supply current is determined by the external clock. when internal cr are selected, the power- supply current will be a value of adding curr ent consumption of internal cr oscillator (i crh , i crl ) to the specified value. in on-chip debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumpt ion therefore increases accordingly. ? refer to ?(1) clock timing? in ?4. ac characteristics? for f ch and f cl . ? refer to ?(2) source clock/machine clock? in ?4. ac characteristics? for f mp and f mpl . *3 : when a low voltage detection circuit stop bit (lvd cr2: lvdstp set) is not set to ?1?, the power supply current will be the sum of the current consumpt ion value for a low voltage detection circuit (i lv d 2 ) and the specified value. parameter symbol pin name condition value unit remarks min typ max power supply current* 2 i ccts * 3 vcc (external clock operation) f ch = 10 mhz, time-base timer mode t a = +25 c ? 0.5 0.9 ma i cch * 3 sub stop mode t a = +25 c ? 11 110 a i lvd1 v cc consumption current using a low voltage interrupt circuit only ? 510 a i lvd2 current consumption using a low voltage detection reset circuit and an fram power supply monitor circuit only ? 25 50 a i crh current consumption of internal main cr oscillator ? 70 100 a i crl at oscillating 100 khz current consumption of internal sub cr oscillator ? 920 a
MB95R203A ds07-12630-2e 25 4. ac characteristics (1) clock timing (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name condi- tion value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 10 mhz when the main oscillation circuit is used x0, x1, hclk1, hclk2 1 ? 20 mhz when the main external clock is used f crh ? 0.96 1 1.04 mhz when the main internal cr clock is used ( + 5 c t a + 35 c) 7.2 (tbd) ? 8.8 (tbd) f cl x0a, x1a ? 32.768 ? mhz when the sub oscillation circuit is used ? 32.768 ? khz when the sub external clock is used f crl ? 50 100 200 khz when the sub internal cr clock is used clock cycle time t hcyl x0, x1 100 ? 1000 ns when the main oscillation circuit is used x0, x1, hclk1, hclk2 50 ? 1000 ns when the main external clock is used t lcyl x0a, x1a ? 30.5 ? s when using sub clock input clock pulse width t wh1 x0, hclk1, hclk2 20 ?? ns when the external clock is used, the duty ratio should range between 40% and 60% t wl1 t wh2 x0a ? 15.2 ? s t wl2 input clock rise time and fall time t cr x0, x0a, hclk1, hclk2 ?? 5ns when the external clock is used t cf internal cr oscillation start time t crhwk ??? 10 s when the main internal cr clock is used t crlwk ??? 50 s when the sub internal cr clock is used
MB95R203A 26 ds07-12630-2e t hcyl t wh1 t cr 0.2 v cc x0, hclk1, hclk2 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 x0 x1 f ch x0 f ch x1 ? figure of main clock input port external connection when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.2 v cc x0a 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl2 x0a x1a f cl x0a f cl x1a ? figure of sub clock input port external connection when using a crystal or ceramic oscillator when using external clock open
MB95R203A ds07-12630-2e 27 (2) source clock/machine clock (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine cloc k division ratio selection bit (sycc : div1 and div0) . this source clock is divided by t he machine clock division ratio sele ction bit (sycc : div1 and div0) , and it becomes the machine clock. further, t he source clock can be selected as follows. ? main clock divided by 2 ? main cr clock ? sub clock divided by 2 ? sub cr clock divided by 2 *2 : operation clock of the microcontrolle r. machine clock can be selected as follows. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 (clock before division) t sclk ? 100 ? 2000 ns when using main external clock min : f ch = 20 mhz, divided by 2 max : f ch = 1 mhz, divided by 2 125 ? 1000 ns when using main cr oscillation clock min : f crh = 8 mhz max : f crh = 1 mhz ? 61 ? s when using sub oscillation clock f cl = 32.768 khz, divided by 2 ? 20 ? s when using sub oscillation clock f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 10 mhz when using main oscillation clock 1 ? 8 mhz when using main cr oscillation clock f spl ? 16.384 ? khz when using sub oscillation clock ? 50 ? khz when using sub cr clock machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 100 ? 32000 ns when using main oscillation clock min : f sp = 10 mhz, no division max : f sp = 0.5 mhz, divided by 16 100 ? 16000 ns when using main cr clock min : f sp = 10 mhz, no division max : f sp = 1 mhz, divided by 16 61 ? 976.5 s when using sub oscillation clock min : f spl = 16.384 khz, no division max : f spl = 16.384 khz, divided by 16 20 ? 320 s when using sub cr clock min : f spl = 50 khz, no division max : f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 10 mhz when using main oscillation clock 0.0625 ? 8 mhz when using main cr clock f mpl 1.024 ? 16.384 khz when using sub oscillation clock 3.125 ? 50 khz when using sub cr clock
MB95R203A 28 ds07-12630-2e f ch (main oscillation) f crh (internal main cr clock) f cl (sub oscillation) f crl (internal sub cr clock) sclk (source clock) division circuit x 1 x 1/4 x 1/8 x 1/16 mclk (machine clock) clock mode select bit (sycc2:rcs1, rcs0) divided by 2 divided by 2 divided by 2 ? outline of clock generation block 3.6 2.7 1. 8 16 khz 10 mhz ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) (without on chip debug function) source clock frequency (f sp /f spl ) operating voltage (v) a/d converter operation range 3.6 2.7 16 khz 10 mhz ? operating voltage - operating frequency ( t a = + 5 c to + 35 c) (with on chip debug function) source clock frequency (f sp ) operating voltage (v) a/d converter operation range
MB95R203A ds07-12630-2e 29 (3) external reset (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation time of oscillator is the time that the am plitude reaches 90%. in the crys tal oscillator, the oscillation time is between several ms and tens of ms. in cera mic oscillators, the oscillation time is between hundreds of s and several ms. in the external cl ock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 100 ? s at stop mode, sub clock mode, sub sleep mode, and watch mode 100 ? s at time-base timer mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 100 s rst x0 ? at normal operating ? at stop mode, sub clock mode, su b sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabil ization wait time execute instruction
MB95R203A 30 ds07-12630-2e (4) power-on reset (vss = 0.0 v, t a = ? 40 c to + 85 c) note: a sudden change the power supply voltage may activate the power-on rese t function. when changing power supply voltages during operation, set the slope of rising within 30 mv/ms. ? time from power-on to user pr ograming operation (reset release) parameter symbol conditions value unit remarks min max power supply rising time t r ? 0.1 50 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on parameter symbol conditions value unit min typ max reset release time t rst ?? 21 ? ms 0.2 v 0.2 v t off t r 1.6 v 0.2 v v cc v cc v dl+ t rst low voltage detection reset release voltage internal reset reset release time power-on reset instruction execution
MB95R203A ds07-12630-2e 31 (5) peripheral input timing (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse t ilih int02 to int07, ec0, ec1 2 t mclk * ? ns peripheral input ?l? pulse t ihil 2 t mclk * ? ns t ilih int02 to int07, ec0, ec1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
MB95R203A 32 ds07-12630-2e (6) uart/sio, serial i/o timing (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for details on t mclk . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc uck internal clock operation output pin : c l = 80 pf + 1 ttl. 4 t mclk * ? ns uck uo time t slov uck, uo ? 190 + 190 ns valid ui uck t ivsh uck,ui 2 t mclk * ? ns uck valid ui hold time t shix uck, ui 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck external clock operation output pin : c l = 80 pf + 1 ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck 4 t mclk * ? ns uck uo time t slov uck, uo 0 190 ns valid ui uck t ivsh uck, ui 2 t mclk * ? ns uck valid ui hold time t shix uck, ui 2 t mclk * ? ns t scyc t ivsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v uck uo ui 0.8 v t slsh t ivsh t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v uck uo ui 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? internal shift clock mode ? external shift clock mode
MB95R203A ds07-12630-2e 33 (7) i 2 c timing (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistance and l oad capacitance of the scl and sda lines. *2 : the maximum value of t hd;dat is applicable only if the device does not extend the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. parameter symbol pin name conditions value unit standard- mode fast-mode min max min max scl clock frequency t scyc scl r = 1.7 k , c = 50 pf* 1 01000400khz (repeat) start condition hold time sda scl t hd;sta scl sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta scl sda 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl sda 03.45* 2 00.9* 2 s data setup time sda scl t su;dat scl sda 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl sda 4.0 ? 0.6 ? s bus free time between stop condition and start condition t buf scl sda 4.7 ? 1.3 ? s sda scl t wakeup t low t high t hd;sta t hd;dat t su;dat t su;sta t su;sto t buf t hd;sta
MB95R203A 34 ds07-12630-2e (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condi- tions value * 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k , c = 50 pf* 1 (2 + nm / 2) t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm / 2) t mclk ? 20 (nm / 2) t mclk + 20 ns master mode start condition hold time t hd;sta scl sda ( ? 1 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl sda (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode start condition setup time t su;sta scl sda (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl sda (2 nm + 4) t mclk ? 20 ? ns data hold time t hd;dat scl sda 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl sda ( ? 2 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between cleaning interrupt and scl rising t su;int scl (nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl sda 4 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception
MB95R203A ds07-12630-2e 35 (continued) (vcc = 3.3 v, vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistance and load capacitance of the scl and sda lines. *2 : ? refer to ? (2) source clock/ma chine clock? for details on t mclk . ? m is the cs4 and cs3 bits (bit4 and bit3) of the i 2 c clock control register (iccr0) . ? n is the cs2 to cs0 bits (bit2 to bit0) of the i 2 c clock control register (iccr0) . ? the actual i 2 c timing is determined by the machine (t mclk ) and the values of m and n configured in bits cs4 to cs0 of the i 2 c clock control register (iccr0) . ? standard-mode : m and n can be set in the range : 0.9 mhz < t mclk (machine clock) < 10 mhz. the machine clock to be used is determin ed by the settings of m and n as follows. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) , : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) , : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 1 mhz ? fast-mode : m and n can be set in the range : 3.3 mhz < t mclk (machine clock) < 10 mhz. the machine clock to be used is determin ed by the settings of m and n as follows. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter symbol pin name condi- tions value * 2 unit remarks min max stop condition detection t su;sto scl sda r = 1.7 k , c = 50 pf* 1 4 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception restart condition detection condition t su;sta scl sda 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception bus free time t buf scl sda 2 t mclk ? 20 ? ns during reception data hold time t hd;dat scl sda 2 t mclk ? 20 ? ns in slave transmission mode data setup time t su;dat scl sda t low ? 3 t mclk ? 20 ? ns in slave transmission mode data hold time t hd;dat scl sda 0 ? ns during reception data setup time t su;dat scl sda t mclk ? 20 ? ns during reception sda scl (when using wakeup function) t wakeup scl sda oscillation sta- bilization wait time + 2 t mclk ? 20 ? ns
MB95R203A 36 ds07-12630-2e (8) low voltage detection (v ss = 0.0 v, t a = ? 40 c to + 85 c) * : ls1 and ls0 mean the ls1 bit and the ls0 bit (bit1 an d bit0) for the low voltage detection interrupt control register (lvdcr) respectively. parameter symbol value unit remarks min typ max low voltage detection reset release voltage v dl + 1.75 1.85 1.95 v at power-supply rise detection voltage v dl ? 1.65 1.75 1.85 v at power-supply fall hysteresis width v hys 70 100 ? mv fram power supply monitor release voltage v dl + 1.8 1.9 2.0 v at power-supply rise detection voltage v dl ? 1.7 1.8 1.9 v at power-supply fall hysteresis width v hys 70 100 ? mv low voltage detection interrupt release voltage v dl + 2.2 2.3 2.4 v at ls1 = 0, ls0 = 0, power- supply rise* 2.4 2.5 2.6 v at ls1 = 0, ls0 = 1, power- supply rise* 2.6 2.7 2.8 v at ls1 = 1, ls0 = 0, power- supply rise* 2.8 2.9 3.0 v at ls1 = 1, ls0 = 1, power- supply rise* detection voltage v dl ? 2.1 2.2 2.3 v at ls1 = 0, ls0 = 0, power- supply fall* 2.3 2.4 2.5 v at ls1 = 0, ls0 = 1, power- supply fall* 2.5 2.6 2.7 v at ls1 = 1, ls0 = 0, power- supply fall* 2.7 2.8 2.9 v at ls1 = 1, ls0 = 1, power- supply fall* hysteresis width v hys 70 100 ? mv power-supply start voltage v off ?? 1.2 v power-supply end voltage v on 2.0 ?? v power-supply voltage change time (at power supply rise) t r 0.3 ?? s slope of power supply that reset release signal generates ? 200 ? s slope of power supply that reset release signal generates within rating (v1 dl + , v2 dl + ) power-supply voltage change time (at power supply fall) t f 0.3 ?? s slope of power supply that reset detection signal generates ? 200 ? s slope of power supply that reset detection signal generates within rating (v1 dl ? , v2 dl ? ) reset release delay time t d1 ?? 300 s reset detection delay time t d2 ?? 20 s
MB95R203A ds07-12630-2e 37 v hys t d2 t d1 t r t f v cc v on v off v dl+ v dl- time internal reset signal time
MB95R203A 38 ds07-12630-2e 5. a/d converter (1) a/d converter electrical characteristics (vcc = 2.7 v to 3.6 v, vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 5.0 ? + 5.0 lsb linearity error ? 3.5 ? + 3.5 lsb differential linear error ? 3.0 ? + 3.0 lsb zero transition voltage v ot v ss ? 1.5 lsb v ss + 0.5 lsb v ss + 4.0 lsb v full-scale transition voltage v fst v cc ? 4.0 lsb v cc ? 1.5 lsb v cc + 0.5 lsb v compare time ? 1.1 ? 27.5 s sampling time ? 0.4 ?? s 2.7 v vcc 3.6 v at external impedance < 1.8 k analog input voltage v ain v ss ? v cc v
MB95R203A ds07-12630-2e 39 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the extern al impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relation- ship between the external impedanc e and minimum sampling time and ei ther adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be sufficient, connect a c apacitor of about 0.1 f to the analog input pin. ? about errors |v cc ? v ss | becomes smaller, values of relative errors grow larger. r c analog input note : the values are reference values. ? analog input equivalent circuit 2.7 v vcc 3.6 v : r : = 5.3 k (max) , c : = 8.5 pf (max) comparator during sampling : on 0 2 4 6 8 10 12 14 16 1 8 20 01234 0 10 20 30 40 50 60 70 8 0 90 100 05 15 10 20 25 30 35 40 [external impedance = 0 k to 100 k ] [external impedance = 0 k to 20 k ] minimum sampling time [ s] external impedance [k ] minimum sampling time [ s] external impedance [k ] ? the relationship between external impedance and minimum sampling time.
MB95R203A 40 ds07-12630-2e (3) definition of a/d converter terms ? resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. ? linearity error (unit : lsb) the deviation between the value along a straig ht line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device a nd the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. ? differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 l sb, from an ideal value. ? total error (unit : lsb) difference between actual and theoretical values, caus ed by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff 3fe 3fd 004 003 002 001 3ff 3fe 3fd 004 003 002 001 1 lsb 0.5 lsb v ot v ss v cc v ss v nt v cc {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = v cc ? v ss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : a voltage at which digital outpu t transits from (n - 1) to n =
MB95R203A ds07-12630-2e 41 (continued) v ( n + 1 ) t ? v nt 1 lsb v ss v cc v ss v cc v ss v cc v nt v ss v cc 001 002 003 004 3fc 3fd 3fe 3ff 001 002 003 004 3fd 3fe 3ff n - 2 n - 1 n n + 1 {1 lsb n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst ( measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n linearity error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst ( measure- ment value) v ot (measurement value) n : a/d converter digital output value v nt : a voltage at which digital output transits from (n - 1) to n. v ot (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc ? 2.0 lsb [v] ideal characteristics = =
MB95R203A 42 ds07-12630-2e 6. fram characteristics *: t a = +25 c parameter value unit remarks min typ max number of read/write cycle ? 10 15 * ? cycle
MB95R203A ds07-12630-2e 43 example characteristics ? power supply current and temperature characteristics (continued) 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 v cc [ v ] i cc [ma] 10 mhz 8 mhz 4 mhz 2 mhz 0 1 2 3 4 5 -50 0 +50 +100 t a [c] i cc [ma] 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 v cc [ v ] i ccs [ma] 10mhz 8 mhz 4mhz 2mhz 0 1 2 3 4 5 -50 0 +50 +100 t a [c] i ccs [ma] 0 50 100 150 200 1.5 2 2.5 3 3.5 4 v cc [ v ] i ccl [ a] 0 50 100 150 200 -50 0 +50 +100 t a [c] i ccl [ a] i cc -v cc t a = + 25 c, f mp = 2, 4, 8, 10 mhz (divided by 2) main clock mode with external clock operating i cc -t a v cc = 3.6 v, f mp = 10 mhz (divided by 2) main clock mode with external clock operating i ccs -v cc t a = + 25 c, f mp = 2, 4, 8, 10 mhz (divided by 2) main sleep mode with the external clock operating i ccs -t a v cc = 3.6v, f mp = 10 mhz (divided by 2) main sleep mode with the external clock operating i ccl -v cc t a = + 25 c, f mpl = 16 khz (divided by 2) sub clock mode with the external clock operating i ccl -t a v cc = 3.6 v,f mpl = 16khz (divided by 2) sub clock mode with the external clock operating
MB95R203A 44 ds07-12630-2e (continued) 0 50 100 150 200 1.5 2 2.5 3 3.5 4 v cc [ v ] i ccls [ a] 0 50 100 150 200 -50 0 +50 +100 t a [c] i ccls [ a] 0 50 100 150 200 1.5 2 2.5 3 3.5 4 v cc [ v ] i cct [ a] 0 50 100 150 200 -50 0 +50 +100 t a [c] i cct [ a] 0 0.5 1 1.5 2 1.5 2 2.5 3 3.5 4 v cc [ v ] i cts [ a] 10mhz 8 mhz 4mhz 2mhz 0 0.5 1 1.5 2 -50 0 +50 +100 t a [c] i cts [ a] i ccls -v cc t a = + 25 c, f mp = 16 khz (divided by 2) sub sleep mode with external clock operating i ccls -t a v cc = 3.6 v,f mpl = 16 khz (divided by 2) sub sleep mode with external clock operating i cct -v cc t a = + 25 c, f mpl = 16 khz (divided by 2) watch mode with external clock operating i cct -t a v cc = 3.6 v,f mpl = 16 khz (divided by 2) watch mode with external clock operating i cts -v cc t a = + 25 c, f mp = 16 khz (divided by 2) timebase timer mode with ex ternal clock operating i cts -t a v cc = 3.6 v,f mp = 10mhz (divided by 2) timebase timer mode with external clock operating
MB95R203A ds07-12630-2e 45 (continued) 0 50 100 150 200 1.5 2 2.5 3 3.5 4 v cc [ v ] i cch [ a] 0 50 100 150 200 -50 0 +50 +100 t a [c] i cch n [ a] 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 v cc [ v ] i ccmcr [ a] 0 1 2 3 4 5 -50 0 +50 +100 t a [c] i ccmcr [ a] 0 50 100 150 200 1.5 2 2.5 3 3.5 4 v cc [ v ] i ccscr [ a] 0 50 100 150 200 -50 0 +50 +100 t a [c] i ccscr [ a] i cch -v cc t a = + 25 c, f mp = (stop) sub stop mode with the external clock operating i cch -t a v cc = 3.6 v,f mpl = (stop) sub stop mode with the external clock stopping i ccmcr -v cc t a = + 25 c, f mp = 1 mhz (no division) main clock mode with internal main cr clock operating i ccmcr -t a v cc = 3.6 v,f mp = 1 mhz (no division) main clock mode with internal main cr clock operating i ccscr -v cc t a = + 25 c, f mp = 50 khz (divided by 2) sub clock mode with intern al main cr clock operating i ccscr -t a v cc =3.6v,f mpl = 50 khz (divided by 2) sub clock mode with internal sub cr clock operating
MB95R203A 46 ds07-12630-2e ? input voltage characteristics 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 v cc [ v ] v ihs / v ils [ v ] 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 v cc [ v ] v ihi / v ili [ v ] v ihs -v cc and v ils -v cc t a = + 25 c v ihi -v cc and v ili -v cc t a = + 25 c
MB95R203A ds07-12630-2e 47 ? output voltage characteristics 0 0.2 0.4 0.6 0. 8 1 i oh [ a] v cc - v oh1 [ v ] 1. 8v 2.0 v 2.7 v 3.0 v 3.6 v v cc -10 - 8 -6 -4 -2 0 0 0.2 0.4 0.6 0. 8 1 -10 - 8 -6 -4 -2 0 i oh [ a] v cc - v oh2 [ v ] 1. 8v 2.0 v 2.7 v 3 v 3.6 v v cc (v cc -v oh1 )-i oh t a = + 25 c (v cc -v oh2 )-i oh t a = + 25 c 0 0.2 0.4 0.6 0. 8 1 0246 8 10 12 i ol [ a] v ol1 [ v ] 1. 8v 2.0 v 2.7 v 3.0 v 3.6 v v cc 0 0.2 0.4 0.6 0. 8 1 0246 8 10 12 i ol [ a] v ol2 [ v ] 1. 8v 2.0 v 2.7 v 3.0 v 3.6 v v cc v ol1 -i ol t a = + 25 c v ol2 -i ol t a = + 25 c
MB95R203A 48 ds07-12630-2e ? pull-up characteristics 0 20 40 60 8 0 100 1.5 2 2.5 3 3.5 4 v cc [ v ] r pull [k ] r pull -v cc t a = + 25 c
MB95R203A ds07-12630-2e 49 ordering information part number package remarks MB95R203Ap-g-sh-jne2 24-pin plastic dip (dip-24p-m07) MB95R203Apf-g-jne2 20-pin plastic sop (fpt-20p-m09)
MB95R203A 50 ds07-12630-2e package dimensions please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 24-pin plastic sdip lead pitch 1.77 8 mm package w idth package length 6.40 mm 22. 8 6 mm sealing method plastic mold mo u nting height 4. 8 0 mm max 24-pin plastic sdip (dip-24p-m07) (dip-24p-m07) c 200 8 -2010 fujitsu semico n ductor limited d24066s-c-1-2 #22. 8 6 0.10(.900 .004) i n dex typ. 7.62(.300) 6.40 0.10 (.252 .004) btm e-mark ? 0.04 +.004 ? .002 .010 0.25 +0.10 1 12 24 13 4. 8 0(.1 8 9)max +0.20 ? 0.30 +.00 8 ? .012 3.00 .11 8 1.77 8 (.070) (.039 . 004) 1.00 0.10 +0.09 ? 0.04 +.004 ? .002 .017 0.43 mi n 0.50(.020) dimensions in mm (inches). n ote: the v al u es in parentheses are reference v al u es n ote 1) pins w idth and pins thickness incl u de plating thickness. n ote 2) pins w idth do not incl u de tie b ar c u tting remainder. n ote 3) # : these dimensions do not incl u de resin protr u sion.
MB95R203A ds07-12630-2e 51 (continued) please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 20-pin plastic sop lead pitch 1.27 mm package w idth package length 7.50 mm 12.70 mm lead shape g u ll w ing lead b end direction n ormal b end sealing method plastic mold mo u nting height 2.65 mm max 20-pin plastic sop (fpt-20p-m09) (fpt-20p-m09) c 200 8 -2010 fujitsu semico n ductor limited f20030s-c-1-2 details of "a" part i n dex 0.10(.004) (.00 8 .004) 0.20 0.10 ? .007 +.005 .099 ? 0.17 +0.13 2.52 (mo u nting height) 0~ 8 (stand off) 0. 8 0 +0.47 ? 0.30 .031 +.019 ? .012 "a" ? .001 +.003 .010 0.25 +0.07 ? 0.02 #12.70 0.10(.500 .004) 11 20 1.27(.050) 1 10 0.25(.010) m ? 0.05 +0.09 0.40 .016 +.004 ? .002 #7.50 0.10 (.295 .004) ? 0.20 +0.40 10.2 .402 +.016 ? .00 8 btm e-mark dimensions in mm (inches). n ote: the v al u es in parentheses are reference v al u es. n ote 1) pins w idth and pins thickness incl u de plating thickness. n ote 2) pins w idth do not incl u de tie b ar c u tting remainder. n ote 3) # : these dimensions do not incl u de resin protr u sion.
MB95R203A 52 ds07-12630-2e major changes in this edition the vertical lines drawn on the left side of the page indicate the changes. page section change results 12 notes on on-chip debug corrected the title. debug on-chip debug added the sentence as follows. ?when you click on the [erase flash memory] and the [target load] button on s oftune workbench,data in the i/o area described below is undefined.?. added the table of address 0070 h , 0071 h . 23 electrical characteristics 3. dc characteristics corrected the condition and th e value of ?open-drain output leak current?. corrected the maximum value of ?pull-up resistance?. 66 80 23, 24 corrected the power supply current. 30 4. ac characteristics (4) power-on reset added ? ? time from power-on to user programing operation (reset release)?. 38 5. a/d converter (1) a/d converter electrical characteristics corrected the value of total error. min : ? 3.0 ? 5.0 max : + 3.0 + 5.0 corrected the value of linearity error. min : ? 2.5 ? 3.5 max : + 2.5 + 3.5 corrected the value of di fferential linear error. min : ? 1.9 ? 3.0 max : + 1.9 + 3.0 corrected the maximum value of zero transition voltage. v ss + 2.5 lsb v ss + 4.0 lsb corrected the minimum value of full-scale transition voltage. v cc ? 3.5 lsb v cc ? 4.0 lsb corrected the value of compare time. min : 0.6 1.1 max : 140 27.5 deleted the item of analog input current. 42 6. fram characteristics corrected the value. min:10 15 ? ? ? typ: ? ? ? 10 15 added the footnote. 43 to 48 example characteristics added a new section.
MB95R203A ds07-12630-2e 53 memo
MB95R203A 54 ds07-12630-2e memo
MB95R203A ds07-12630-2e 55 memo
MB95R203A fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/se rvices/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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